When routing high-speed differential pairs parallel to each other, a constant distance should be maintained between them. This distance helps to achieve the specified differential impedance. The designer should minimize the area in which the specified spacing is enlarged due to pad entries. The differential pairs should be routed symmetrically.
The designer should not place any components or vias between differential pairs even if the signals are routed symmetrically as shown in figure (10). Placement of components and vias between differential pairs could lead to EMC problems and impedance discontinuities.
Figure 10: Do not include any components or vias in-between a differential.
Some high-speed differential pairs need serial coupling capacitors. These capacitors should be placed symmetrically. The capacitors and the pads produce impedance discontinuities. Capacitor sizes such as 0402 are preferable over 0603. Larger packages such as 0805 or C-packs must be avoided.
Figure 11: Place coupling capacitors symmetrically
Since the vias introduce an enormous discontinuity in impedance, the number of vias must be reduced and should be placed symmetrically.
Figure 12: Place vias symmetrically.
While routing a differential pair, both the traces should be routed on the same layer so that the impedance requirements are met as shown in figure (13). Also, the same number of vias should be included in the traces.
Figure 13: Route pairs on the same layer and place the same number of vias.
The high-speed interfaces have additional requirements concerning the time of arrival at a destination known as clock skew between different traces and pairs of signals. For instance, in a high-speed parallel bus, all data signals need to arrive within a time period in order to meet the setup and hold time requirements of the receiver. The PCB designer should ensure that such permitted skew is not exceeded. To achieve this requirement, the length matching is necessary.
The differential pair signals demand a very tight delay skew between the positive and negative signal traces. Hence, any length differences should be compensated by using serpentines. The geometry of serpentine traces should be carefully designed as shown in figure (14) to reduce impedance discontinuity.
Figure 14: Use this recommended serpentine trace geometry.
The designer should place the serpentine traces at the root of the length mismatch. This ensures that the positive and negative signal components are propagated synchronously over the connection as shown in figure (15).
Figure 15: Add length correction to the mismatching point at the source.
The bends are usually the source of length mismatches. The compensation should be planted very close to the bend with a maximum distance of 15mm as shown in the below figure (16).
Figure 16: Place length compensation close to the bends.
Generally, two bends compensate each other. If the bends are closer than 15mm then no additional compensation with serpentines is necessary. The signals should not traverse asynchronously over a distance of more than 15mm.
Figure 17: Bends can compensate each other
The mismatches in each segment of a differential pair connection should be matched individually. In figure (18) shown below, the vias separate the differential pair into two segments. The bends need to be compensated individually here. This ensures that the positive and negative signals are propagated synchronously through the vias. The DRC overlooks this violation since it only checks the length difference over the whole connection.
Figure 18: Length differences should be compensated in each segment.
The signal speed is not the same in all the layers of a PCB. Since it is hard to figure out the difference, it is preferable to route signals on the same layer if they need to be matched.
Figure 19: Pairs within the same interface should be preferably routed on the same layer.
Some of the CAD tools also consider the trace length inside a pad to its total length. The figure shown below depicts two layouts which are similar from an electrical point of view.
In figure (20) on the left, the traces inside the capacitor pads do not have an equal length. Even though the signals are not using the internal traces, some CAD tools consider this as part of the length calculation and display a length difference between the positive and negative signals. In order to minimize this, ensure that the pad entry is equal for both signals.
In the same way, some CAD tools do not consider the length of vias when calculating the total length. Since differential pairs should have the same amount of vias in both traces, the error does not affect the length matching. However, it can affect calculations for matching two differential pairs or the matching of parallel buses.
Figure 20: Pay attention to length calculation issues encountered in some CAD tools.
Asymmetric breakout of differential pair signal is preferred as shown in figure (21), wherever possible in order to avoid the serpentine traces.
Figure 21: Symmetric breakout of differential pair
Small loops can be included for the shorter trace instead of serpentine traces if there is enough space between pads. This is generally preferred over a serpentine trace.
Figure 22: Preferred breakout of differential pairs.
An incorrect signal return path results in noise coupling and EMI issues. The designer should always think of the signal return path when routing a signal. The power rails and low-speed signals take the shortest return current path as shown in figure (23). In contrast to this, the return current of high-speed signals tries to follow the signal path.
Figure 23: In high-speed PCB, the return current tries to follow the signal path.
A signal should not be routed over a split plane as the return path is not able to follow the signal trace. Refer figure (24). If a plane is split between a sink and source, route the signal trace around it. If the forward and return paths of a signal are separated, the area between them acts as a loop antenna.
Stitching capacitors should be incorporated if a signal needs to be routed over two different reference planes. The stitching capacitor enables the return current to travel from one reference plane to the other. The capacitor should be placed close to the signal path so that the distance between the forward and return path are kept small. Generally, the values of stitching capacitors are between 10nF and 100nF.
Figure 24: Placement of stitching capacitors over split planes.
In general, plane obstructions and plane slots must be avoided. If it is really necessary to route over such obstruction then stitching capacitors should be used as shown in figure (25).
Figure 25: Stitching capacitors incorporated when routing over plane obstructs.
The designer should look out for voids (no copper area) in reference planes while routing high-speed signals. Voids in reference planes are generated when placing vias close together as shown in figure (25). Large void areas should be avoided by ensuring adequate separation between vias. It is better to place fewer ground and power vias in order to reduce via voids.
Figure 26: Avoid via plane voids.
The return path should be considered at the source and sink of a signal. In figure (27) shown below, the left design is considered to be a bad design. Since there is only one single ground via on the source side, the return current cannot travel back over the reference ground plane as intended. The return path is the ground connection present on the top layer instead. The problem in hand is that the impedance of the signal trace is calculated as referenced to the ground plane and not to the ground trace on the top layer. Hence, it is essential to place ground vias at the source and sink side of the signal. This allows the return current to travel back on the ground plane as shown in figure (27) on the right.
Figure 27: Return path should be considered when placing ground vias.
When a power plane is considered as a reference to a signal, then the signal should be able to propagate back over the power plane. The signals are referenced to ground in the source and sink. To switch the reference to the power plane, stitching capacitors should be incorporated at the sink and source. If the sink and source are utilizing the same power rail for their supply, then the bypass capacitors can act as stitching capacitors if they are placed close to the signal start/exit point as shown in figure (28). The ideal value for the stitching capacitor is between 10nF and 100nF.
Figure 28: Use stitching capacitors when using power planes as reference
When a differential signal switches a layer, the reference ground plane will also be switched. Hence, stitching vias should be added close to the layer change vias as shown in figure (29) on the right. This permits the return current to change the ground plane. When dealing with differential signals, the switching ground vias should be placed symmetrically.
Figure 29: Stitching capacitors should be used when signal changes ground reference
When a signal switches to a different layer that has a different reference plane then stitching capacitors should be implemented. This permits the return current to flow from the ground to the power plane through the stitching capacitor as shown in figure 30 on the right. Also, the stitching capacitor placement and routing should be symmetrical when differential pairs are considered.
Figure 30: Incorporate stitching capacitors when signal reference plane changes.
The designer should not route high-speed signals on the edge of the reference planes or close to PCB borders. This can have an adverse impact on the trace impedance.
Figure 31: High-speed signals should not be routed at plane and PCB edges.
Defining separate Analog and Digital ground sections approach makes it easy in the schematic to determine which components and pins should be connected to the digital ground and which ones to the analog ground section. These kinds of designs can be routed by placing two different ground planes as reference. The two planes should be placed accurately. The digital and analog components should be placed underneath the respective sections as shown in figure (32, right).
Figure 32: Power plane splitting needs to be done carefully
The mixed-signal circuits require the analog and digital ground connected at a single point. In the schematics, it is always recommended to place ferrite beads or zero-ohm resistors between the analog and digital ground.
