by Sandeep Sankararaman, Principal Engineer, and Shawn Tucker, Principal SI/RF Engineer, Samtec
As the demand for higher frequencies and wider bandwidths continues its march upward, RF connectors need to keep up with or even exceed device bandwidth demands. Mating the RF connector to a PCB or substrate requires careful consideration of several factors to get the full performance out of the connector. This article provides an understanding of what makes successful launches work and covers design guidelines and an understanding of what knobs to turn to make connector launches perform well up to 100 GHz. As there are so many types of RF connectors, this article focuses on the compression-mount PCB type.
A compression-mount connector is compressed onto a PCB using mounting hardware to make a connection and can connect to either microstrip or stripline traces on the board. With the number of high-speed connections in PCBs increasing continually, compression-mount connectors provide several advantages. They are relatively compact, so several can be placed on a PCB, and as they can be placed anywhere on a PCB, compression-mount connectors can be located near the device the signal needs to reach, and they can also be reused.
The launch includes the connector, signal via, and the via to the trace transition inside the PCB. To accurately gauge the performance of this combination, the tip of the connector and break-out region, including a short section of trace (about 2 mm), must be modeled and optimized together to achieve very broad bandwidths. RF launch designs are complex structures with no closed-form solutions and consist of many elements that need tuning in an EM solver to deliver maximum performance. Each of the sub-components shown in Figure 1 represents a degree of freedom in the design of the launch.
Figure 1: Sub-components of an RF launch
The transition between PCB and connector tip has complex interactions requiring tuning, including contributions from both sides, to achieve the best performance. The connector landing pad size is dictated by the mechanical constraints of the connector and must be large enough to provide a reliable connection by accounting for manufacturing variations of connector and PCB fabrication but small enough to allow for designs to achieve the desired level of performance.
Electrically speaking, the drill hole size is the dimension that matters, not the finished hole size for a via. Having a list of common drill sizes used by the PCB vendor is very useful while trying to tune via launches. The drill size determines the minimum pad size of the via on the inner layers, and the smaller the minimum pad size, the better the via performance. Due to improved registration, laser-drilled micro vias can accommodate very small pad sizes, with an annular ring of as little as 2 mils with an L1:L2 transition (pad diameter = drill diameter + 2x annular ring). For deeper micro vias, the drill size and annular ring must be increased in size.
The tuning feature is used to equalize the impedance from the via pad/void region to the trace. The ground planes under the launch tie the ground rings together. Voids in the planes allow tuning the impedance seen by the signal as it travels down the via. When possible, it is best to create a “ground feature” on power planes and signal layers as it ensures adequate metal coverage along the via, improving the quasi-coaxial structure of the launch and its performance.
There are two rings of ground vias, and the performance of the launch is heavily dependent on them. The inner ring strongly impacts the impedance of the transition and cutoff frequency. The second ground ring helps seal the gaps between the vias of the inner ground ring, which limits crosstalk to adjacent transitions. Tuning the different sub-components to obtain a wide bandwidth launch requires balancing several competing constraints.
When using a through via to transition to an internal layer, there is a stub created by the part of the via that extends below the transition layer. The higher the bandwidth goal, the more this stub impacts the performance. The impact of the stub is worst at a frequency where the stub length equals one-quarter of the wavelength:
Where,
While f o is the frequency at which the impact is most prominent, the via stub starts to degrade the performance of the via transition well before this frequency because it adds additional capacitance to the launch.
A common strategy to minimize the via stub’s impact is to drill away most of the stub. In the back-drilling process, the PCB fabricator drills out the via stub from the side opposite the connector launch. However, no manufacturing process is perfect, and the back drill cannot get close to the signal launch layer for fear of damaging the contact between the via and trace.
Therefore, a residual stub is always left behind after the back-drilling process. There is also a tolerance associated with the leftover stub length. For example, a PCB fabricator might say the leftover stub length can be 8 mils +/-4 mil. A back-drilled via, in this case, can be left with a stub that is anywhere between 4 and 12 mils long, which is quite a large range. To be fair, this is a conservative example of stub length variation, and in many cases, smaller stubs may be achievable.
Figure 2: Via stub length impact on return loss
To illustrate the need to push for the smallest stub length, see the curves in Figure 2. There are 16 curves in the graph, each one corresponding to a stub length between 0 and 15 mils. The smaller the stub length, the higher the return loss across the band. To better visualize bandwidth impact, the frequency at which the return loss crosses the 15 dB level (VSWR = 1.4:1) is plotted in Figure 3. There are two main points to consider about the shape of the curve. First, the curve is not linear, with longer stub lengths causing a rapid drop-off in the bandwidth of the via transition, and for small stub lengths, the reduction in bandwidth is not significant.
Figure 3: Bandwidth impact of via stubs of different lengths
So, pushing for a small residual stub and a tight tolerance provides significant benefits not only from the point of view of increasing the operating bandwidth of the launch but also from the point of view of all launches on the board behaving similarly to one another.
Thus far, only the impact of a single stub has been considered, but every internal trace has at least two stubs, one at the launch and the other at the device side. So, any performance degradation introduced by the stub will be magnified by the reflections set up between the stubs at either end of the trace, as depicted in Figure 4. For each of the three stub lengths depicted in the figure, the return loss impact of reflections bouncing between two via launches at either end of the 3-in.-long, low-loss trace is shown in solid lines. The dashed line shows the comparative performance of a single launch, and in every case, it is significantly better than the double via case.
Figure 4: Multiple reflections between via stubs at either end of a trace magnify any performance limitations introduced by the via stub.
The best mitigation strategy is to go with laser vias with no stub at all. However, if back-drilled vias must be used, it is possible to compensate for the capacitance introduced by the stub to a limited extent in the design of the launch. In designing the compensation structure, it might be tempting to compensate for the worst-case stub length, but this can still result in poor performance if the stub tolerance is large. Figure 5 clarifies this, where a tolerance of 4 mils on the 6 mil stub is assumed. The launch compensation is designed to provide the best impedance match for the worst-case stub length of 10 mils.
Figure 5: Impact of stub tolerance on compensation design
For a 10 mil stub, the impedance of the launch is within 1 ohm of nominal. The problem arises for vias with the stub length at the other end of the tolerance (2 mils). For this stub length, the launch looks quite inductive. Keep in mind that every stub on the board need not be the same length. The +/-4 mil tolerance can result in some vias looking inductive and others not, even when they are adjacent launches.
The inner ground ring has a strong influence on the performance of the launch. Two main factors determine the diameter of the inner GND via ring:
Figure 6: Equations to help with sizing the inner GND ring
The impedance of the launch area: Figure 6 shows that the impedance of the launch area can be determined to the first order by treating the signal drill size as the center conductor diameter of the coax and the inner GND ring diameter as the shield diameter of coax. The nominal system impedance (e.g., 50 ohms) can be used as the target impedance for long vias.Short vias, however, are strongly impacted by the capacitive loading caused by the interaction between the launch and the end of the connector body. For this reason, a higher target Z o, such as 70 ohms, is better. That way, the average effect of the connector + launch via is closer to 50 ohms.
The cutoff frequency of the higher order modes supported by the launch: Normally, in a launch for a coaxial RF connector, only the fundamental mode to propagate is desired, which is the transverse electromagnetic mode (TEM). Above the cutoff frequency, the launch can support higher-order modes. When this happens, energy is spread among the different modes, and as the modes propagate differently, the signal gets distorted quickly. To prevent this, the launch needs to be designed so the cutoff frequency lies outside the bandwidth of interest.
Figure 7 shows that the cutoff frequency is inversely proportional to the GND ring’s size and the dielectric constant seen when traveling down the via. The higher these numbers are, the lower the cutoff frequency and the lower the operating bandwidth of the launch. The formula for fcutoff in Figure 7 provides the cutoff frequency in GHz when the diameters (Dv, DGND) are given in inches.
Figure 7: Dielectric constant in PCBs is direction dependent
Figure 8: Higher order modes cutoff frequency as a function of drill diameter and ER
Both the impedance and the cutoff frequency are also inversely proportional to the dielectric constant (eR) seen by the signal as it travels down the via. It is important to note that this eR need not match the value seen by the trace. The reason is that PCBs are formed of laminates bonded together as composites and consist of glass fiber and resin. Figure 8 shows a cross-sectional picture of a PCB.
There are both core layers and prepreg layers, each consisting of layers of glass cloth and resin. Since each of these layers has different dielectric properties, the effective dielectric constant seen by the signal depends on the direction it travels. In other words, PCBs are anisotropic as far as the dielectric constant is concerned. The higher the anisotropy, the greater the difference in dielectric constant seen by the via as compared to the trace.
To achieve wide-bandwidth launches, the dielectric constant of both the resin and the glass should be low and equal. This ensures the lowest possible dielectric constant around the via and, therefore, the highest cutoff frequency. The table in Figure 9 shows that to reach cutoff frequencies higher than 90 GHz, signal drill diameters of less than 5 mils and dielectric constants of less than 3.1 are needed. The values in Figure 9 can serve as a useful starting point in guiding the design of an RF launch.
Figure 9: Rapid degradation in performance near and past the cutoff frequency of a launch
Figure 10: Physical structure of signal and GND vias of a launch (left) and conceptual drawing of the different physical parts of the launch structure (right)
Figure 9 makes it possible to understand mathematically why the performance of the launch quickly degrades around the cutoff frequency, as seen in Figure 10. To get a physical explanation of what is happening, refer to Figure 11. The structure of the launch via and the surrounding GND vias is shown on the left side of the figure. The portion of the vias colored in green represents the portion that the signal energy should travel in. As the GND vias are through vias, they continue below the reference layer of the trace to form waveguide structures below the signal reference layers.
Figure 11: Electric field patterns in the launch area below and above the cutoff frequency
To better visualize this, a conceptual schematic is shown on the right half of Figure 11 that shows that the connector launches the energy into the coaxial portion of the launch with the signal energy then propagating down a stripline. However, below the trace reference layer, the GND vias form a circular waveguide under the signal via. The plane layers form several rectangular vias and stitch GND vias under the trace reference layer. The circular waveguide and rectangular waveguides under the trace are non-TEM structures, so they cannot propagate energy below the cutoff.
Figure 12: Plot of loss factor allows determination of whether launch performance is being impacted by higher order
