Designing a PCB is a challenging task, which becomes even more complex when high-speed signals are involved. To assist PCB designers, we have compiled a list of best practices for routing high-speed PCBs to help achieve an optimal design.
The best practice is to have a continuous ground plane beneath signal traces. Ideally, the PCB should be a four-layer board with one layer dedicated entirely to the ground plane. This approach minimizes impedance between different grounding points on the PCB and reduces the potential for noise.
Improperly placed vias can create areas with increased current density. The best method is to position vias in a grid pattern, ensuring enough space for power planes to pass through.
Trace bends should be kept to a minimum. If bends are necessary, it is recommended to use 135° bends instead of 90° bends.
A minimum spacing of four times the trace width should be maintained between adjacent copper traces in the same net. Each bend segment should be 1.5 times the trace width. Most PCB design software of does not automatically check these minimum spacing requirements.
Traces should have sufficient spacing to minimize crosstalk. The level of crosstalk depends on the length and spacing between two traces. In some areas, routing paths may create bottlenecks where traces are closer than desired. In such situations, the spacing between signals should be immediately increased outside the bottleneck. Even when the minimum requirement is met, further increasing the spacing can be beneficial.
Long stubs can act as antennas and cause EMC issues. Stubs with improper routing can also create reflections that negatively affect signal integrity.
If such traces are necessary, route signals in a closed loop, as shown in the diagram.
Differential signals should be kept at a consistent distance and routed symmetrically. This distance helps achieve the specified differential impedance. Designers PCB should minimize the area where specified spacing is increased due to pad clearances.
No components or vias should be placed between differential pairs, even if the signals are routed symmetrically. Placing components and vias between differential pairs could lead to EMC issues and impedance discontinuities.
Since vias introduce significant impedance discontinuities, their number should be minimized and placed symmetrically.
When routing differential pairs, both traces should be routed on the same layer to meet impedance requirements. The same number of vias should also be included in the routing paths.
Incorrect signal return paths result in noise coupling and EMI problems. Designers should always consider the return path of a signal when routing it. Power paths and low-speed signals take the shortest return current path. However, for high-speed signals, the return current should always follow the signal path.
A signal should not be routed across a split plane, as the return path cannot follow the signal trace. If a plane divides the start and endpoint of a signal, the signal path should be routed around it. If the forward and return paths are separated, the area between them behaves like a loop antenna.
Solution: Decoupling Capacitors
These should be used if a signal must be routed across two different reference planes.
A decoupling capacitor allows return current to pass from one reference plane to another.
Designers should avoid routing high-speed signals near the edges of reference planes or PCB boundaries, as this can negatively impact trace impedance.
To minimize noise, analog and digital ground planes should be separated. Mixed-signal circuits require both planes to be connected at a single point, ideally near the main integrated circuit.
It is always recommended to place ferrite beads or zero-ohm resistors between the analog and digital sections in schematics. In mixed-signal designs with split planes, digital signals should not be routed across the analog ground plane, and analog signals should not be routed across the digital ground plane.
To achieve optimal high-speed performance, trace width should match component size. The ideal trace width depends on the required impedance. To reduce impedance tuning issues between the signal path and components, careful adjustments must be made.
