By Dirk Stans – Eurocircuits and Geert Willems – Center for Electronics Design & Manufacturing, imec
[1] PBA Design-for-Manufacturing Guideline EDM-D-001: PCB Specification, imec-cEDM, July 2013.
[2] IPC-4101C: Specification for Base Materials for Rigid and Multilayer Boards
[3] Geert Willems, Piet Watté, Predicting PCB delamination in lead-free assembly, Global SMT & Packaging, Vol. 10, No. 9, September 2010, p. 10.
There are a host of material parameters to consider for the current generation of PCB designs:
They determine whether or not your PCB will delaminate and the vias will survive the lead-free assembly conditions applied to your PCB.
How do you select the right combination for your design?
One could select the best possible value for each parameter but this limits the number of available materials considerably. Furthermore, these materials have their own disadvantages such as a poor manufacturability and brittleness.
Your PCB supply is expensive and not future safe.
To provide a cost effective and scientifically sound solution to its customers Eurocircuits partnered with imec’s Center for Electronics Design & Manufacturing. The methodology presented here is described in detail in PBA Design-for-Manufacturing Guideline: EDM-D-001: PCB Specification, developed by imec/cEDM and available at www.cedm.be. Parts of the guideline are reproduced here with permission of imec/cEDM.
Your product will be soldered lead-free so you need lead-free soldering compatible FR-4. The requirements for the PCB laminate depend on:
Your internal or external assembly partners should be able to provide the answer to the first question. Your customer or the end-user is the source to find the answer to the other questions.
How to determine the number of soldering temperature cycles to a PCB? The answer is given in the table below, Ref. [1].
The PCB fabrication and assembly processes given in the first column determine the number of solder cycles to be taken into account.
Always start from an internationally accepted standard. The IPC standard that defines lead-free solderable FR-4 is IPC-4101C:
More detailed information can be obtained via www.ipc.org
Rather than specifying a base material to your PCB supplier, check that his materials conform to one of the IPC defined classes and see what minimum values he guarantees for these key parameters. Your boards will be cheaper and available faster.
Let”s compare the SnPb era FR-4 against the lead-free compatible FR-4 in respect of these key parameters.
Typical values of SnPb-era FR4 laminate materials compared to those of the lead-free compatible FR4 classes .
As the table shows, there are significant differences between older FR4 and current lead-free solderable FR4s (shown in IPC classes) for the key parameters Td, T260, T288 and CTEz.
We now solder 25-35°C hotter than in tin-lead solder times. This causes risks for:
Let”s further examine the effect of these parameters.
Delamination (extended separation inside the PCB)
Not more than 25 % of the distance between adjacent conductors or plated-through holes.
Not more than 1% of the printed wiring area on each side may be affected.
No propagation as a result of thermal stress testing or representative condition.
(6A) shows separation between two glass weave layers in the base material. The separation can also occur between the base material and the copper foil.
(6B) shows a separation between individual layers.
(6C)and (6D) show separations between laminate and internal or external pads respectively, or copper planes.
T260-T288-T300 determine how long your base material can resist these temperatures before the material starts to delaminate (the material will increase in thickness).
Research and modeling by imec-cEDM has proven, Ref. [1, 2], that the IPC /sheet boundary conditions – especially the fixed T260=30min does not provide sufficient protection to delamination. The following IPC-4101 compatible definition of thermal performance classes guarantees the indicated number Nd of solder cycles without cohesive delamination, Ref. [1]. Note the more stringent T260 and T288 requirements.
A mid performance material with a T260=50min and a T288=10min will be able to withstand at least 12 solder cycles before delamination will occur in the bulk of the laminate assuming the PCB is dry. The physico-chemical mechanism links Td, T260 and T288. Therefore, the actual Td value is not an additional parameter.
Graphs to determine the number of solder cycles to delamination for a given combination of Time-to-delamination and decomposition temperatures are given respectively in EDM-D-001 and Ref. [2]. A calculation tool is available at www.cedm.be (free use for cEDM members).
A via crack is usually caused by the difference in thermal expansion between the laminate and the copper barrel of the hole. This is influenced by the thickness of the board, the thickness of the copper plating and the diameter of the hole. The key material parameters for this is the CTEz value.
Via cracks due to thermal stress can appear during soldering or during the operation of the board. Soldering stress cracks are tested by repeated soldering and for operational lifetime one tests this effect through accelerated thermal cycling testing (typical -40 o C/125 o C).
Let’s concentrate on the most critical effect of temperature cycling: z-axis tension in the via barrel due to the much larger Coefficient of Thermal Expansion CTE of the laminate in the z-axis compared to the CTE=17ppm/o C of copper.
The material parameter that has the biggest impact on cyclic tension in the z-axis direction is the CTEz value.
In the graph above you can see the relationship between the z-axis expansion of the material (CTEz) and temperature. The expansion is a rather linear process but has a click point where the angle of the curve changes and the z-axis expansion increases faster per °C. This click point is at the Tg value of the base material. It is actually the way the Tg is determined using Thermo-Mechanical Analysis (TMA).
The graph also shows that a traditional FR-4 material with Tg=150°C (orange line) has a CTEz value which is a lot higher than for the new lead-free solderable material (light green line) with the same Tg value. This is achieved by reducing the CTE of the laminate through the use of inert fillers (increases drill wear!) or/and using higher functionality epoxy types (harder, more brittle materials).
Conclusion: CTEz is far more important than Tg with respect to z-axis expansion. A higher Tg material does not guarantee a higher thermal performance with respect to lead-free soldering. However, it will increase the PCB cost.
According to EDM-D-001, 4.4.3, Ref. [1], plastic via deformation dominates under soldering conditions. Therefore, the via lifetime (number of solder cycles to failure) depends mainly on the CTEz value of the laminate. The small dependency on the via dimensions can be neglected for specification purposes. EDM-D-001 provides CTEz based criteria for selecting laminates that will provide sufficient number of solder cycles to via failure.
Eurocircuits materials with a maximum CTEz=3.5% guarantee conservatively less than 1% via failure after 14 solder cycles.
Note that under soldering conditions the vias are stretched by several percent which is a very large mechanical load knowing that via barrels will immediately fail when stretched by 7 to 10%, Ref. [1], Appendix B.
Under operational conditions the dimensions, board thickness and plating thickness may have a significant impact on the lifetime. In general the stress increases and thus the lifetime decreases with increasing board thickness, decreasing via diameter and decreasing plating thickness. Imec/cEDM developed an accurate analytical model to calculate the via strain during thermal cycling and to estimate the via lifetime.
The graphs below show the dependency of the via strain under -40/125 o C cycling for a laminate with a1=50ppm/o C, an board thickness D and via diameter d for t=20µm (left) and t=10µm (right)
